Advances in computing technology presently make it possible to perform trillions of computational operations per second on data sets that are sometimes as large as a trillion bytes. These advances can be largely attributed to the exponential increase in the operating speed and complexity of integrated circuits (ICs). Unfortunately, this increase in operating speed and complexity has been accompanied by a corresponding increase in power consumption. This increase in power consumption can create problems for mobile computing devices, because mobile computing devices usually suffer from stringent power constraints due to limited battery life. Note that within these devices, a large portion of the battery power is converted into thermal energy during normal system operation. As the IC technology continues to advance, this power consumption is increasingly becoming a limiting factor for performance in mobile computing devices.
One of the main sources of power consumption within a computing device is the memory subsystem. A typical memory subsystem may include a memory controller IC chip (“controller chip” hereafter) coupled to one or more memory IC chips (“memory chips” hereafter) through a signaling interface. For example, FIG. 1 presents a block diagram illustrating an embodiment of a typical memory subsystem 100, which includes a controller 102 coupled to a multi-bank memory chip 104 through a signaling interface 106. While FIG. 1 illustrates memory subsystem 100 having one controller chip and four memory banks 108, other embodiments may have additional controller chips and/or fewer or more memory banks 108. In one embodiment, controller 102 and memory chip 104 are implemented on the same integrated circuit (IC) die. In other embodiments, they may be implemented on different integrated circuits.
Advances in signaling technology have dramatically lowered the amount of energy required to transport information between the controller chips and the memory chips. For example, the “per-bit” transport energy over the signaling interface 106 can be reduced from approximately 60 picoJoules (pJ) to approximately 3 pJ by using advanced signaling technology. However, the energy dissipation within memory chip 104, particularly when memory chip 104 is implemented as dynamic random access memory (DRAM) devices, has remained relatively high. For example, the energy dissipation during a memory cell (inside memory banks 108) access is approximately 72 pJ per bit for the DRAM devices disposed on a state-of-the-art small-outline dual-inline memory module (SODIMM). Note that energy dissipation inside the memory core continues to increase as memory devices operate at increasingly higher frequencies.
Hence, there is a need to provide a technique to reduce energy dissipation during memory core operations.